1. Technical Field
The disclosure relates in general to a reconfigurable instruction encoding method and a processor architecture.
2. Background
A conventional processor builds in an instruction table, and a compiler transforms to-be-executed instructions into machine codes for the processor to perform corresponding behavior. However, the instruction table is universal, and it is not optimized for any individual application. Consequently, it results in dramatic variations between signal phases of consecutive execution instructions transmitted via the instruction bus after multiple execution instructions of one single application are compiled and assembled. The dramatic variations induce rapid changes of the signal logic level at a CMOS circuit input terminal, and leads to huge power consumption.
If the processor is still during the design level, the instruction table can be re-designed to be more suited to some applications. However, for a design-completed processor, a re-designed instruction table will cause compatibility problems, so that the machine codes from the compiler can not be executed by the processor designed based on an original instruction table. Besides, the applications develop rapidly and variously, the built-in and unchangeable instruction table might not meet the performance of all the newly-developed applications.